1. Field of the Invention
The present invention relates to a printed circuit board having a buried pattern and a method of manufacturing the same.
2. Description of the Related Art
A printed circuit board (PCB) serves to electrically connect electronic parts to each other, supply power and mechanically fix them thereon through a wire pattern formed on an insulation substrate made of a phenol resin, an epoxy resin or the like. Such a printed circuit board includes a one-sided printed circuit board, in which a wiring pattern is formed on only one side of an insulation substrate, a double-sided printed circuit board, in which wiring patterns are formed on both sides of an insulation substrate, and a multi-layered printed circuit board (MLB), in which wiring patterns are provided in multiple layers.
As a method of forming a wiring pattern on a printed circuit board, an additive process, a subtractive process, a semi additive process (SAP), a modified semi additive process (MSAP) or the like is used.
Recently, with the advancement of the electronics industry, electronic parts are increasingly required to be highly functionalized and to be miniaturized. In response to the trend, printed circuit boards loaded with such electronic parts are also required to have a highly densified circuit pattern. Thus, methods of realizing various fine circuit patterns are developed, proposed and applied.
In the present invention, among the methods of forming a fine circuit pattern, a method of realizing the densification of a circuit pattern by burying a circuit pattern in an insulation layer will be described.
FIG. 1 shows a conventional process of forming a wiring pattern using MSAP or SAP.
First, as shown in FIG. 1A, a seed layer 3 is formed on an insulation substrate 1, and then a plating resist layer 5 is formed on the seed layer 3. Thereafter, an electroplating layer is formed on the seed layer 3 through an electroplating process. Subsequently, as shown in FIG. 1B, the plating resist layer 5 is removed from the seed layer 3, and then, as shown in FIG. 1C, the exposed portion of the seed layer 3 is removed from the insulation substrate 1 through flash etching or quick etching to form a wiring pattern 7.
However, when the exposed portion of the seed layer 3 is removed from the insulation substrate 1 through flash etching or quick etching, the electroplating layer for forming the wiring pattern is also etched, so that the lateral face of the wiring pattern 7 is greatly tapered and the width of the wiring pattern 7 is decreased, with the result that the wiring pattern 7 is short-circuited and the signal transfer characteristics of the wiring pattern 7 are weakened.